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AMC: Advanced Multi-accelerator Controller

Author
Hussain, T.; Haider, A.; Gursal, S.; Ayguade, E.
Type of activity
Journal article
Journal
Parallel computing
Date of publication
2015-01
Volume
41
First page
14
Last page
30
DOI
https://doi.org/10.1016/j.parco.2014.10.003 Open in new window
Repository
http://hdl.handle.net/2117/78376 Open in new window
URL
http://www.sciencedirect.com/science/article/pii/S0167819114001264 Open in new window
Abstract
The rapid advancement, use of diverse architectural features and introduction of High Level Synthesis (HLS) tools in FPGA technology have enhanced the capacity of data-level parallelism on a chip. A generic FPGA based HLS multi-accelerator system requires a microprocessor (master core) that manages memory and schedules accelerators. In a real environment, such HLS multi-accelerator systems do not give a perfect performance due to memory bandwidth issues. Thus, a system demands a memory manager a...
Citation
Hussain, T., Haider, A., Gursal, S., Ayguade, E. AMC: Advanced Multi-accelerator Controller. "Parallel computing", Gener 2015, vol. 41, p. 14-30.
Keywords
FPGA, HLS, HPC, Master core
Group of research
CAP - High Performace Computing Group

Participants

  • Hussain, Tassadaq  (author)
  • Haider, Amna  (author)
  • Gursal, Shakaib A.  (author)
  • Ayguade Parra, Eduard  (author)

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