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Designing a branch target buffer for executing branches with zero time cost in a RISC processor

Autor
Cortadella, J.; Jové, T.
Tipus d'activitat
Article en revista
Revista
Microprocessing and microprogramming
Data de publicació
1988-08
Volum
24
Número
1-5
Pàgina inicial
573
Pàgina final
580
DOI
https://doi.org/10.1016/0165-6074(88)90113-5 Obrir en finestra nova
URL
http://www.sciencedirect.com/science/article/pii/0165607488901135 Obrir en finestra nova
Resum
The execution of branch instructions causes a loss of performance on pipelined processors. In this paper a new branch mechanism based on a Branch Target Buffer is presented. It executes branches with zero time cost. In order to evaluate its performance improvement for several pipeline structures, an analytical model has been developed and simulations have been performed. The chip area required for its implementation is also considered. The performance increase and the simplicity of its design ma...
Paraules clau
Branch target buffer, RISC
Grup de recerca
ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals

Participants