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Logic decomposition of speed-independent circuits

Author
Kondratyev, A.; Cortadella, J.; Kishinevsky, M.; Lavagno, L.; Yakovlev, A.
Type of activity
Journal article
Journal
Proceedings of the IEEE
Date of publication
1999-02
Volume
87
Number
2
First page
347
Last page
362
DOI
https://doi.org/10.1109/5.740027 Open in new window
Repository
http://hdl.handle.net/2117/126062 Open in new window
URL
https://ieeexplore.ieee.org/document/740027 Open in new window
Abstract
Logic decomposition is a well-known problem in logic synthesis, but it poses new challenges when targeted to speed-independent circuits. The decomposition of a gate into smaller gates must preserve not only the functional correctness of a circuit but also speed independence, i.e., hazard freedom under unbounded gate delays. This paper presents a new method for logic decomposition of speed-independent circuits that solves the problem in two major steps: (1) logic decomposition of complex gates an...
Citation
Kondratyev, A., Cortadella, J., Kishinevsky, M., Lavagno, L., Yakovlev, A. Logic decomposition of speed-independent circuits. "Proceedings of the IEEE", Febrer 1999, vol. 87, núm. 2, p. 347-362.
Keywords
Asynchronous circuits, Hazards, Logic decomposition, Speed indepedence, Technology mapping
Group of research
ALBCOM - Algorithms, Computational Biology, Complexity and Formal Methods

Participants

  • Kondratyev, Alex  (author)
  • Cortadella Fortuny, Jordi  (author)
  • Kishinevsky, Michael  (author)
  • Lavagno, Luciano  (author)
  • Yakovlev, Alex  (author)

Attachments