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Instruction scheduling for a clustered VLIW processor with a word-interleaved cache

Author
Gibert, E.; Sánchez, J.; Gonzalez, A.
Type of activity
Journal article
Journal
Concurrency and Computation: Practice and Experience
Date of publication
2006-09
Volume
18
Number
11
First page
1391
Last page
1411
DOI
https://doi.org/10.1002/cpe.1013 Open in new window
URL
http://onlinelibrary.wiley.com/doi/10.1002/cpe.1013/full Open in new window
Abstract
Clustering is a common technique to overcome the wire delay problem incurred by the evolution of technology. Fully distributed architectures, where the register file, the functional units and the data cache are partitioned, are particularly effective to deal with these constraints and moreover they are very scalable. In this paper, effective instruction scheduling techniques for a word-interleaved cache clustered VLIW processor are presented. Such scheduling techniques rely on (i) loop unrolling...
Keywords
Cache storage, Instruction sets, Multiprocessing systems, Parallel architectures, Processor scheduling
Group of research
ARCO - Microarchitecture and Compilers

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