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Reducing branch delay to zero in pipelined processors

Autor
Gonzalez, A.; Llaberia, J.
Tipus d'activitat
Article en revista
Revista
IEEE transactions on computers
Data de publicació
1993-03
Volum
42
Número
3
Pàgina inicial
363
Pàgina final
371
DOI
https://doi.org/10.1109/12.210179 Obrir en finestra nova
Repositori
http://hdl.handle.net/2117/101127 Obrir en finestra nova
URL
http://ieeexplore.ieee.org/document/210179/ Obrir en finestra nova
Resum
A mechanism to reduce the cost of branches in pipelined processors is described and evaluated. It is based on the use of multiple prefetch, early computation of the target address, delayed branch, and parallel execution of branches. The implementation of this mechanism using a branch target instruction memory is described. An analytical model of the performance of this implementation makes it possible to measure the efficiency of the mechanism with a very low computational cost. The model is use...
Citació
González, A., Llaberia, J. Reducing branch delay to zero in pipelined processors. "IEEE transactions on computers", Març 1993, vol. 42, núm. 3, p. 363-371.
Paraules clau
Buffer storage, Performance evaluation, Pipeline processing
Grup de recerca
ARCO - Microarquitectura i Compiladors
CAP - Grup de Computació d'Altes Prestacions

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