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IATAC: a smart predictor to turn-off L2 cache lines

Author
Abella, J.; Gonzalez, A.; Vera, F.J.; O’Boyle, M.
Type of activity
Journal article
Journal
ACM transactions on architecture and code optimization
Date of publication
2005-03
Volume
2
Number
1
First page
55
Last page
77
DOI
https://doi.org/10.1145/1061267.1061271 Open in new window
URL
http://dl.acm.org/citation.cfm?doid=1061267.1061271 Open in new window
Abstract
As technology evolves, power dissipation increases and cooling systems become more complex and expensive. There are two main sources of power dissipation in a processor: dynamic power and leakage. Dynamic power has been the most significant factor, but leakage will become increasingly significant in future. It is predicted that leakage will shortly be the most significant cost as it grows at about a 5× rate per generation. Thus, reducing leakage is essential for future processor design. Since l...
Group of research
ARCO - Microarchitecture and Compilers

Participants

  • Abella Ferrer, Jaume  (author)
  • Gonzalez Colas, Antonio Maria  (author)
  • Vera Rivera, Francisco Javier  (author)
  • O’Boyle, Michael F.P.  (author)