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A survey of branch techniques in pipelined processors

Autor
Gonzalez, A.
Tipus d'activitat
Article en revista
Revista
Microprocessing and microprogramming
Data de publicació
1993-10
Volum
36
Número
5
Pàgina inicial
243
Pàgina final
257
DOI
https://doi.org/10.1016/0165-6074(93)90263-K Obrir en finestra nova
URL
http://www.sciencedirect.com/science/article/pii/016560749390263K Obrir en finestra nova
Resum
This paper presents a review and a classification of mechanisms for reducing the cost of branches in pipelined processors. We show that the wide spectrum of different mechanisms proposed in the literature are based on just few techniques that in each case are combined to build the particular mechanism. The basis of these techniques are explained and many examples of real cases are given using most of the latest commercial and academic processors.
Paraules clau
Branch instructions, Computer architecture, Instruction dependencies, Pipelined processors
Grup de recerca
ARCO - Microarquitectura i Compiladors

Participants