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Control speculation for energy-efficient next-generation superscalar processors

Author
Aragon, J.; González, J.; Gonzalez, A.
Type of activity
Journal article
Journal
IEEE transactions on computers
Date of publication
2006-03
Volume
55
Number
3
First page
281
Last page
291
DOI
https://doi.org/10.1109/TC.2006.32 Open in new window
Repository
http://hdl.handle.net/2117/100841 Open in new window
URL
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=1583558 Open in new window
Abstract
Conventional front-end designs attempt to maximize the number of "in-flight" instructions in the pipeline. However, branch mispredictions cause the processor to fetch useless instructions that are eventually squashed, increasing front-end energy and issue queue utilization and, thus, wasting around 30 percent of the power dissipated by a processor. Furthermore, processor design trends lead to increasing clock frequencies by lengthening the pipeline, which puts more pressure on the branch predict...
Citation
Aragón, J., González, J., González, A. Control speculation for energy-efficient next-generation superscalar processors. "IEEE transactions on computers", Març 2006, vol. 55, núm. 3, p. 281-291.
Keywords
Control speculation, Energy-aware systems, Low-power design, Processor architecture
Group of research
ARCO - Microarchitecture and Compilers

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