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Exploiting narrow values for soft error tolerance

Author
Ergin, O.; Unsal, O.; Vera, F.J.; Gonzalez, A.
Type of activity
Journal article
Journal
IEEE computer architecture letters
Date of publication
2006-07
Volume
5
Number
2
First page
45
Last page
48
DOI
https://doi.org/10.1109/L-CA.2006.12 Open in new window
Repository
http://hdl.handle.net/2117/102025 Open in new window
URL
http://ieeexplore.ieee.org/abstract/document/4069169/ Open in new window
Abstract
Soft errors are an important challenge in contemporary microprocessors. Particle hits on the components of a processor are expected to create an increasing number of transient errors with each new microprocessor generation. In this paper we propose simple mechanisms that effectively reduce the vulnerability to soft errors in a processor. Our designs are generally motivated by the fact that many of the produced and consumed values in the processors are narrow and their upper order bits are meanin...
Citation
Ergin, O., Unsal, O., Vera, X., González, A. Exploiting narrow values for soft error tolerance. "IEEE computer architecture letters", Juliol 2006, vol. 5, núm. 2, p. 45-48.
Keywords
Cache storage, Error correction, Hardware, Impurities, Manufacturing, Microprocessors, Multithreading, Neutrons, Process design, Random access memory
Group of research
ARCO - Microarchitecture and Compilers

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