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Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems

Author
Roca, A.; Hernandez, C.; Lodde, M.; Flich Cardo, José
Type of activity
Journal article
Journal
Computers and electrical engineering
Date of publication
2015-07-01
Volume
45
First page
374
Last page
385
DOI
https://doi.org/10.1016/j.compeleceng.2015.04.020 Open in new window
Repository
http://hdl.handle.net/2117/85389 Open in new window
URL
http://www.sciencedirect.com/science/article/pii/S0045790615001494 Open in new window
Abstract
Manycore CMP systems are expected to grow to tens or even hundreds of cores. In this paper we show that the effective co-design of both, the network-on-chip and the coherence protocol, improves performance and power meanwhile total area resources remain bounded. We propose a snoopy-aware network-on-chip topology made of two mesh-of-tree topologies. Reducing the complexity of the coherence protocol - and hence its resources - and moving this complexity to the network, leads to a global decrease i...
Citation
Roca, A., Hernandez, C., Lodde, M., Flich Cardo, José. Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems. "Computers and electrical engineering", 01 Juliol 2015, vol. 45, p. 374-385.
Keywords
COHERENCE, Chip multiprocessor, Coherence protocol, NETWORK, Network architecture, Network-on-chip, SWITCH
Group of research
ALBCOM - Algorithms, Computational Biology, Complexity and Formal Methods

Participants

  • Roca Perez, Antoni  (author)
  • Hernandez Gañan, Carlos  (author)
  • Lodde, Mario  (author)
  • Flich Cardo, José  (author)

Attachments