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RTL synthesis: From logic synthesis to automatic pipelining

Author
Cortadella, J.; Galceran, M.; Kishinevsky, M.; Sapatnekar, S.
Type of activity
Journal article
Journal
Proceedings of the IEEE
Date of publication
2015-11-01
Volume
103
Number
11
First page
2061
Last page
2075
DOI
https://doi.org/10.1109/JPROC.2015.2456189 Open in new window
Project funding
Computational Models and Methods for Massive Structured Data
Repository
http://hdl.handle.net/2117/82027 Open in new window
URL
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7275092 Open in new window
Abstract
Design automation has been one of the main propellers of the semiconductor industry with logic synthesis being one of the core technologies in this field. This article reviews the evolution of logic synthesis until the advent of techniques for automatic pipelining based on elastic timing, either synchronous or asynchronous. The emergence of these techniques can enable a productive interaction with tools that can do microarchitectural exploration of complex designs.
Citation
Cortadella, J., Galceran, M., Kishinevsky, M., Sapatnekar, S. RTL synthesis: From logic synthesis to automatic pipelining. "Proceedings of the IEEE", 01 Novembre 2015, vol. 103, núm. 11, p. 2061-2075.
Keywords
Architectural pipelining, Design automation, High-level synthesis, Logic synthesis, Timing elasticity
Group of research
ALBCOM - Algorithms, Computational Biology, Complexity and Formal Methods

Participants

  • Cortadella Fortuny, Jordi  (author)
  • Galceran Oms, Marc  (author)
  • Kishinevsky, Michael  (author)
  • Sapatnekar, Sachin S.  (author)

Attachments