Loading...
Loading...

Go to the content (press return)

Test escapes of stuck-open faults caused by parasitic capacitances and leakage currents

Author
Arumi, D.; Rodriguez-Montanes, R.; Figueras, J.
Type of activity
Journal article
Journal
IEEE transactions on very large scale integration (VLSI) systems
Date of publication
2015-09-24
Volume
24
Number
5
First page
1739
Last page
1748
DOI
https://doi.org/10.1109/TVLSI.2015.2477103 Open in new window
Repository
http://hdl.handle.net/2117/86699 Open in new window
URL
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7275171 Open in new window
Abstract
Intragate open defects are responsible for a significant percentage of defects in present technologies. A majority of these defects causes the logic gate to become stuck open, and this is why they are traditionally modeled as stuck-open faults (SOFs). The classical approach to detect the SOFs is based on a two-vector sequence, and has been proved effective for a wide range of technologies. However, factors typically neglected in past technologies have become a major concern in nanometer technolo...
Citation
Arumi, D., Rodriguez, R., Figueras, J. Test escapes of stuck-open faults caused by parasitic capacitances and leakage currents. "IEEE transactions on very large scale integration (VLSI) systems", 24 Setembre 2015, vol. 24, núm. 5, p. 1739-1748.
Keywords
Integrated circuit (IC) testing, leakage currents, parasitic capacitances, stuck-open faults (SOFs), test escapes
Group of research
QINE - Low Power Design, Test, Verification and Security ICs

Participants

Attachments