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Manich Bou, Salvador

Total activity: 168

Areas of expertise: Hardware Security of ICs, IC digital design, Low power digital design, Test of ICs

University degree: Enginyer Industrial
Doctoral courses: Enginyer Industrial
Professional category: Associate professor

Research group: QINE - Low Power Design, Test, Verification and Security ICs
Department: Department of Electronic Engineering
School: Barcelona School of Industrial Engineering (ETSEIB)

E-mail: salvador.manichupc.edu
Contact details: UPC directory

Orcid: 0000-0001-5265-1209

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Scientific and technological production

1 to 50 of 168 results

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Electronics
Manich, S.
Collaboration in journals

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IEEE transactions on information forensics and security
Manich, S.
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IEEE transactions on computers
Manich, S.
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Cryptography
Manich, S.
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Hardening digital circuits against Invasive attacks with on-chip delay measurements
Theses

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The variability challenge in nano-cmos and beyond-cmos: novel ic design paradigms for mitigation and exploitation
Rodriguez-Montanes, R.; Rubio, A.; Aragones, X.; Altet, J.; Moll, F.; Mateo, D.; Calomarde, A.; Manich, S.; Arumi, D.; Vourkas, I.; Ntinas, V.
Competitive project

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Remote sensing
Manich, S.
Collaboration in journals

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Impact of laser attacks on the switching behavior of RRAM devices
Arumi, D.; Manich, S.; Álvaro Gómez-Pau; Rodriguez-Montanes, R.; Montilla, V.; Hernández, D.; Bargalló, M.; Campabadal, F.
Electronics
Vol. 9, num. 1, p. 1-9
DOI: 10.3390/electronics9010200
Date of publication: 2020-01-20
Journal article

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IEEE transactions on information forensics and security
Manich, S.
Collaboration in journals

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Sensors
Manich, S.
Collaboration in journals

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IEEE transactions on information forensics and security
Manich, S.
Collaboration in journals

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Electronics
Manich, S.
Collaboration in journals

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IET circuits, devices and systems
Manich, S.
Collaboration in journals

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Sensors
Manich, S.
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Applied sciences
Manich, S.
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IEEE transactions on information forensics and security
Manich, S.
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IEEE transactions on computer-aided design of integrated circuits and systems
Manich, S.
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Electronics
Manich, S.
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Electronics
Manich, S.
Collaboration in journals

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IEEE transactions on computer-aided design of integrated circuits and systems
Manich, S.
Collaboration in journals

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IEEE transactions on information forensics and security
Manich, S.
Collaboration in journals

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Sensors
Manich, S.
Collaboration in journals

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Sensors
Manich, S.
Collaboration in journals

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IET circuits, devices and systems
Manich, S.
Collaboration in journals

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Sensors
Manich, S.
Collaboration in journals

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Applied sciences
Manich, S.
Collaboration in journals

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Hardware Level Security Techniques Against Reading of Cache Memory Sensitive Data
Neagu, M.; Manich, S.
Date of publication: 2019-02-07
Book chapter

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Applied sciences
Manich, S.
Collaboration in journals

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A calibratable detector for invasive attacks
Weiner, M.; Wieser, W.; Lupon, E.; Sigl, G.; Manich, S.
IEEE transactions on very large scale integration (VLSI) systems
Vol. 27, num. 5, p. 1067-1079
DOI: 10.1109/TVLSI.2019.2892408
Date of publication: 2019-01-25
Journal article

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Sensors
Manich, S.
Collaboration in journals

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Sensors
Manich, S.
Collaboration in journals

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Unpredictable bits generation based on RRAM parallel configuration
Arumi, D.; Álvaro Gómez-Pau; Manich, S.; Rodriguez-Montanes, R.; Bargalló, M.; Campabadal, F.
IEEE electron device letters
Vol. 40, num. 2, p. 341-344
DOI: 10.1109/LED.2018.2886396
Date of publication: 2018-12-12
Journal article

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Applied sciences
Manich, S.
Collaboration in journals

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Random Bit Generation Based on The Association of Serial CBRAM Devices
Arumi, D.; Manich, S.; Rodriguez-Montanes, R.
Workshop on Secure Hardware and Security Evaluation
Presentation's date: 2018-03-22
Presentation of work at congresses

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Computers
Manich, S.
Collaboration in journals

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SGR - Suport a Grups de Recerca - QINE - Disseny de Baix Consum, Test, Verificació i Circuits Integrats de Seguretat
Rodriguez-Montanes, R.; Arumi, D.; Manich, S.; Balado, L.; Lupon, E.
Competitive project

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Sensors
Manich, S.
Collaboration in journals

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Crypto-Test-Lab for security validation of ECC co-processor test infrastructure
Lupon, E.; Rodriguez-Montanes, R.; Manich, S.
Conference on Design of Circuits and Integrated Systems
p. 1-6
DOI: 10.1109/DCIS.2017.8311632
Presentation's date: 2017-11-22
Presentation of work at congresses

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Design and validation of a platform for electromagnetic fault injection
Balasch, J.; Arumi, D.; Manich, S.
Conference on Design of Circuits and Integrated Systems
p. 1-6
DOI: 10.1109/DCIS.2017.8311630
Presentation's date: 2017-11-22
Presentation of work at congresses

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The low area probing detector as a countermeasure against invasive attacks
Weiner, M.; Manich, S.; Rodriguez-Montanes, R.; Sigl, G.
IEEE transactions on very large scale integration (VLSI) systems
num. 99, p. 1-12
DOI: 10.1109/TVLSI.2017.2762630
Date of publication: 2017-11-07
Journal article

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SELF-HEALING AND SECURE LOW-POWER MEMORY SYSTEMS
Department of Electronic Engineering, Universitat Politècnica de Catalunya
Theses

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Defending cache memory against cold-boot attacks boosted by power or EM radiation analysis
Neagu, M.; Manich, S.
Microelectronics journal
Vol. 62, p. 85-98
DOI: 10.1016/j.mejo.2017.02.010
Date of publication: 2017-04
Journal article

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Electronics
Manich, S.
Collaboration in journals

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Electronics
Manich, S.
Vol. 6, num. 1
Collaboration in journals

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RRAM Based Random Bit Generation for Hardware Security Applications
Arumi, D.; Rodriguez-Montanes, R.; Manich, S.; Pehl, M.
Conference on Design of Circuits and Integrated Systems
p. 1-6
DOI: 10.1109/DCIS.2016.7845382
Presentation's date: 2016-11-25
Presentation of work at congresses

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The SALVADOR simulation framework
Weiner, M.; Arumi, D.; Manich, S.
Conference on Trustworthy Manufacturing and Utilization of Secure Devices
p. 1-2
Presentation's date: 2016-11-15
Presentation of work at congresses

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Random masking interleaved scrambling technique as a countermeasure for DPA/DEMA attacks in cache memories
Neagu, M.; Rodriguez-Montanes, R.; Arumi, D.; Manich, S.
Conference on Trustworthy Manufacturing and Utilization of Secure Devices
p. 21
Presentation's date: 2016-11-14
Presentation of work at congresses

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RRAM based cell for hardware security applications
Arumi, D.; Manich, S.; Rodriguez-Montanes, R.
IEEE International Verification and Security Workshop
p. 7-12
DOI: 10.1109/IVSW.2016.7566599
Presentation's date: 2016-07
Presentation of work at congresses

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IET circuits, devices and systems
Manich, S.
Collaboration in journals

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Circuits and Systems
Manich, S.
Collaboration in journals

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Manich Bou, Salvador

Scientific and technological production

Open Access activity

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