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Value compression to reduce power in data caches

Author
Aliagas, C.; Molina, C.; García, M.; Tubella, J.; Gonzalez, A.
Type of activity
Report
Date
2003-02
Code
UPC-DAC-2003-10
Abstract
Cache memory represents an important percentage of the total energy consumption of today¿s processors. This paper proposes a novel cache design based on data compression to reduce the power dissipation of the data cache. The new scheme stores the same amount of information as a conventional cache but in a smaller physical storage. At the same time, the cache latency is preserved, thus no performance penalty is introduced. The benefits in terms of power reduction vary from 15.5% to 16%, and the ...
Group of research
ARCO - Microarchitecture and Compilers

Participants