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A Performance and area efficient architecture for intrusion detection systems

Author
Sreekar Shenoy, G.; Tubella, J.; Gonzalez, A.
Type of activity
Report
Date
2008-12
Code
701
Abstract
We propose a novel storage that enables us to pipeline the processing of consecutive bytes accessing the upper-most level of the state machine.
Group of research
ARCO - Microarchitecture and Compilers

Participants