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Future vector microprocessor extensions for data aggregations

Author
Hayes, T.; Palomar, O.; Unsal, O.; Cristal, A.; Valero, M.
Type of activity
Presentation of work at congresses
Name of edition
43rd International Symposium on Computer Architecture
Date of publication
2016
Presentation's date
2016-06-18
Book of congress proceedings
43rd International Symposium on Computer Architecture, ISCA 2016: 18-22 June 2016, Seoul, South Korea: proceedings
First page
418
Last page
430
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
DOI
https://doi.org/10.1109/ISCA.2016.44 Open in new window
Project funding
FP7-IDEAS-ERC-321253
High performance computing VII
Repository
http://hdl.handle.net/2117/90618 Open in new window
URL
http://ieeexplore.ieee.org/document/7551411/ Open in new window
Abstract
As the rate of annual data generation grows exponentially, there is a demand to aggregate and summarise vast amounts of information quickly. In the past, frequency scaling was relied upon to push application throughput. Today, Dennard scaling has ceased and further performance must come from exploiting parallelism. Single instruction-multiple data (SIMD) instruction sets offer a highly efficient and scalable way of exploiting data-level parallelism (DLP). While microprocessors originally offered...
Citation
Hayes, T., Palomar, O., Unsal, O., Cristal, A., Valero, M. Future vector microprocessor extensions for data aggregations. A: Annual International Symposium on Computer Architecture. "43rd International Symposium on Computer Architecture, ISCA 2016: 18-22 June 2016, Seoul, South Korea: proceedings". Seul: Institute of Electrical and Electronics Engineers (IEEE), 2016, p. 418-430.
Keywords
Data models, Instruction sets, Registers, Support vector machines
Group of research
CAP - High Performace Computing Group

Participants

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