Loading...
Loading...

Go to the content (press return)

An energy-efficient memory unit for clustered microarchitectures

Author
Bieschewski, S.; Parcerisa, Joan-Manuel; Gonzalez, A.
Type of activity
Journal article
Journal
IEEE transactions on computers
Date of publication
2016-08-01
Volume
65
Number
8
First page
2631
Last page
2637
DOI
https://doi.org/10.1109/TC.2015.2493518 Open in new window
Project funding
Microarchitecture and Compilers for Future Processors III
Repository
http://hdl.handle.net/2117/90303 Open in new window
URL
http://ieeexplore.ieee.org/document/7303897/?arnumber=7303897 Open in new window
Abstract
Whereas clustered microarchitectures themselves have been extensively studied, the memory units for these clustered microarchitectures have received relatively little attention. This article discusses some of the inherent challenges of clustered memory units and shows how these can be overcome. Clustered memory pipelines work well with the late allocation of load/store queue entries and physically unordered queues. Yet this approach has characteristic problems such as queue overflows and allocat...
Citation
Bieschewski, S., Parcerisa, Joan-Manuel, González, A. An energy-efficient memory unit for clustered microarchitectures. "IEEE transactions on computers", 1 Agost 2016, vol. 65, núm. 8, p. 2631-2637.
Keywords
Cache memories, Clustered architectures, Distributed architectures, Microprocessors, Parallel architectures, Store buffer
Group of research
ARCO - Microarchitecture and Compilers

Participants

Attachments