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CRC-based memory reliability for task-parallel HPC applications

Author
Subasi, O.; Unsal, O.; Labarta, J.; Yalcin, G.; Cristal, A.
Type of activity
Presentation of work at congresses
Name of edition
IEEE 30th International Parallel and Distributed Processing Symposium
Date of publication
2016
Presentation's date
2016-05
Book of congress proceedings
2016 IEEE International Parallel and Distributed Processing Symposium (IPDPS 2016): Chicago, Illinois, USA: 23-27 May 2016
First page
1101
Last page
1112
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
DOI
https://doi.org/10.1109/IPDPS.2016.70 Open in new window
Repository
http://hdl.handle.net/2117/91341 Open in new window
Abstract
Memory reliability will be one of the major concerns for future HPC and Exascale systems. This concern is mostly attributed to the expected massive increase in memory capacity and the number of memory devices in Exascale systems. For memory systems Error Correcting Codes (ECC) are the mostcommonly used mechanism. However state-of-the art hardware ECCs will not be sufficient in terms of error coverage for future computing systems and stronger hardware ECCs providing more coverage have prohibitive...
Citation
Subasi, O., Unsal, O., Labarta, J., Yalcin, G., Cristal, A. CRC-based memory reliability for task-parallel HPC applications. A: IEEE International Symposium on Parallel and Distributed Processing. "2016 IEEE International Parallel and Distributed Processing Symposium (IPDPS 2016): Chicago, Illinois, USA: 23-27 May 2016". Chicago, Illinois: Institute of Electrical and Electronics Engineers (IEEE), 2016, p. 1101-1112.
Keywords
Application programs, Cyclic redundancy check, Data flow analysis, Dataflow model, Error correction, Error correction capability, Errors, Hardware, Hardware acceleration, Mathematical analysis, Memory reliability, Reconfigurable hardware, Reliability, Software-based solutions, Task parallelism
Group of research
CAP - High Performace Computing Group

Participants