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Quantitative characterization of the software layer of a HW/SW co-designed processor

Author
Cano, J.; Kumar, R.; Brankovic, A.; Pavlou, D.; Stavrou, K.; Gibert, E.; Martínez, A.; Gonzalez, A.
Type of activity
Presentation of work at congresses
Name of edition
2016 IEEE International Symposium on Workload Characterization
Date of publication
2016
Presentation's date
2016-09
Book of congress proceedings
Proceedings of the 2016 IEEE International Symposium on Workload Characterization: September 25-27, 2016 Providence, RI, USA
First page
138
Last page
147
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
DOI
https://doi.org/10.1109/IISWC.2016.7581274 Open in new window
Repository
http://hdl.handle.net/2117/99687 Open in new window
URL
http://ieeexplore.ieee.org/document/7581274/ Open in new window
Abstract
HW/SW co-designed processors currently have a renewed interest due to their capability to boost performance without running into the power and complexity walls. By employing a software layer that performs dynamic binary translation and applies aggressive optimizations through exploiting the runtime application behavior, these hybrid architectures provide better performance/watt. However, a poorly designed software layer can result in significant translation/optimization overheads that may offset...
Citation
Cano, J., Kumar, R., Brankovic, A., Pavlou, D., Stavrou, K., Gibert, E., Martínez, A., González, A. Quantitative characterization of the software layer of a HW/SW co-designed processor. A: IEEE International Symposium on Workload Characterization. "Proceedings of the 2016 IEEE International Symposium on Workload Characterization: September 25-27, 2016 Providence, RI, USA". Providence, Rhode Island: Institute of Electrical and Electronics Engineers (IEEE), 2016, p. 138-147.
Keywords
Dynamic binary translation, HW/SW codesigned processor, Hardware-software codesign, Hardware-software codesigned processor, Hybrid architectures, Microarchitectural resources, Microprocessor chips, Optimisation, Optimization overheads, Quantitative characterization, Runtime application behavior, Software layer design, Software layer performance, Translation overheads
Group of research
ARCO - Microarchitecture and Compilers

Participants

  • Cano Reyes, Jose  (author and speaker )
  • Kumar, Rakesh  (author and speaker )
  • Brankovic, Aleksandar  (author and speaker )
  • Pavlou, Demos  (author and speaker )
  • Stavrou, Kyriakos  (author and speaker )
  • Gibert Codina, Enric  (author and speaker )
  • Martínez, Alejandro  (author and speaker )
  • Gonzalez Colas, Antonio Maria  (author and speaker )

Attachments