Loading...
Loading...

Go to the content (press return)

An ultra low-power hardware accelerator for automatic speech recognition

Author
Yazdani, R.; Segura, A.; Arnau, J.; Gonzalez, A.
Type of activity
Presentation of work at congresses
Name of edition
49th Annual IEEE/ACM Symposium on Microarchitecture
Date of publication
2016
Presentation's date
2016-10-17
Book of congress proceedings
Proceedings of the 49th IEEE/ACM Symposium on Microarchitecture
First page
580
Last page
591
Publisher
IEEE Press
DOI
https://doi.org/10.1109/MICRO.2016.7783750 Open in new window
Repository
http://hdl.handle.net/2117/105093 Open in new window
URL
http://ieeexplore.ieee.org/document/7783750/ Open in new window
Abstract
Automatic Speech Recognition (ASR) is becoming increasingly ubiquitous, especially in the mobile segment. Fast and accurate ASR comes at a high energy cost which is not affordable for the tiny power budget of mobile devices. Hardware acceleration can reduce power consumption of ASR systems, while delivering high-performance. In this paper, we present an accelerator for large-vocabulary, speaker-independent, continuous speech recognition. It focuses on the Viterbi search algorithm, that represent...
Citation
Yazdani, R., Segura, A., Arnau, J., González, A. An ultra low-power hardware accelerator for automatic speech recognition. A: Annual IEEE/ACM International Symposium on Microarchitecture. "Proceedings of the 49th IEEE/ACM Symposium on Microarchitecture". Taipei: IEEE Press, 2016, p. 580-591.
Keywords
Microprocessor chips, Parallel architectures, Power aware computing, Power consumption, Search problems, Speech recognition, Storage management
Group of research
ARCO - Microarchitecture and Compilers

Participants

Attachments