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RRAM variability and its mitigation schemes

Author
Pouman, P.; Amat, E.; Hamdioui, S.; Rubio, A.
Type of activity
Presentation of work at congresses
Name of edition
PATMOS 2016, Workshop on Power and Timing Modeling, Optimization and Simulation
Date of publication
2016
Presentation's date
2016-09-22
Book of congress proceedings
Proceedings PATMOS 2016
First page
141
Last page
146
DOI
https://doi.org/10.1109/PATMOS.2016.7833679 Open in new window
Project funding
TEC2013-45638-C3-2-R - APROXIMACION MULTINIVEL AL DISEÑO ORIENTADO A LA FIABILIDAD DE CIRCUITOS INTEGRADOS ANALOGICOS Y DIGITALES
Repository
http://hdl.handle.net/2117/103892 Open in new window
URL
http://ieeexplore.ieee.org.recursos.biblioteca.upc.edu/document/7833679/ Open in new window
Abstract
Emerging technologies such as RRAMs are attracting significant attention due to their tempting characteristics such as high scalability, CMOS compatibility and non-volatility to replace the current conventional memories. However, critical causes of hardware reliability failures, such as process variation due to their nano-scale structure have gained considerable importance for acceptable memory yields. Such vulnerabilities make it essential to investigate new robust design strategies at the circ...
Citation
Pouman, P., Amat, E., Hamdioui, S., Rubio, A. RRAM variability and its mitigation schemes. A: International Workshop on Power and Timing Modeling, Optimization and Simulation. "Proceedings PATMOS 2016". Dresden: 2016, p. 141-146.
Keywords
Emerging memory, Mitagation, Process variability, RRAM, Reliability, Resistive memory
Group of research
HIPICS - High Performance Integrated Circuits and Systems

Participants

  • Pouman, Peyman  (author and speaker )
  • Amat Bertran, Esteve  (author and speaker )
  • Hamdioui, Said  (author and speaker )
  • Rubio Sola, Jose Antonio  (author and speaker )

Attachments