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Crossbar-based memristive logic-in-memory architecture

Author
Papandroulikadis, G.; Vourkas, I.; Abustelema, A.; Sirakoulis, G.; Rubio, A.
Type of activity
Journal article
Journal
IEEE transactions on nanotechnology
Date of publication
2017-04-01
Volume
16
Number
3
First page
491
Last page
501
DOI
https://doi.org/10.1109/TNANO.2017.2691713 Open in new window
Project funding
Multilevel approach to the reliability-aware design of analog and digital integrated circuits
Repository
http://hdl.handle.net/2117/104473 Open in new window
URL
http://ieeexplore.ieee.org.recursos.biblioteca.upc.edu/document/7893787/ Open in new window
Abstract
The use of memristors and resistive random access memory (ReRAM) technology to perform logic computations, has drawn considerable attention from researchers in recent years. However, the topological aspects of the underlying ReRAM architecture and its organization have received less attention, as the focus has mainly been on device-specific properties for functionally complete logic gates through conditional switching in ReRAM circuits. A careful investigation and optimization of ...
Citation
Papandroulikadis, G., Vourkas, I., Abustelema, A., Sirakoulis, G., Rubio, A. Crossbar-based memristive logic-in-memory architecture. "IEEE transactions on nanotechnology", 1 Abril 2017, vol. 16, núm. 3, p. 491-501.
Keywords
Computing, Crossbar, Digital logic, Memristor, QQ, Resistive RAM (ReRAM), Resistive switch
Group of research
HIPICS - High Performance Integrated Circuits and Systems

Participants

  • Papandroulikadis, Georgios  (author)
  • Vourkas, Ioannis  (author)
  • Abustelema, Angel  (author)
  • Sirakoulis, Georgios  (author)
  • Rubio Sola, Jose Antonio  (author)

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