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Decoupled state-execute architecture

Autor
Pericàs, M.; Cristal, A.; González, R.; Veidenbaum, A.; Valero, M.
Tipus d'activitat
Article en revista
Revista
Lecture notes in computer science
Data de publicació
2008
Volum
4759
Pàgina inicial
68
Pàgina final
78
DOI
https://doi.org/10.1007/978-3-540-77704-5_6 Obrir en finestra nova
URL
https://link.springer.com/chapter/10.1007/978-3-540-77704-5_6 Obrir en finestra nova
Resum
The majority of register file designs follow one of two well–known approaches. Many modern high-performance processors (POWER4 [1] , Pentium4 [2]) use a merged register file that holds both architectural and rename registers. Other processors use a Future File (eg, Opteron [3]) with rename registers kept separately in reservation stations. Both approaches have issues that may limit their application in future microprocessors. The merged register file scales poorly in terms of power- performanc...
Grup de recerca
CAP - Grup de Computació d'Altes Prestacions

Participants

  • Pericàs, Miquel  (autor)
  • Cristal Kestelman, Adrián  (autor)
  • González, Rubén  (autor)
  • Veidenbaum, Alexander V.  (autor)
  • Valero Cortes, Mateo  (autor)