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A fine grain queueing model for multi–core multi–threaded architectures

Author
Zilan, R.; Verdu, J.; Garcia, J.; Milito, R.; Nemirovsky, M.; Valero, M.
Type of activity
Report
Date
2010
Code
UPC-DAC-RR-CAP-2010-11
Abstract
Multi-core multi-threaded architectures are increasing the amount of hardware resources on chips to exploit the performance of systems with large number of parallel running threads. The resources are hierarchically distributed in the processor to reduce sources of contention among threads that share a particular hardware unit. This design advance also leads to new challenges in the system performance analysis, since the cost of simulation-based experiments exponentially scales with the complexit...
Group of research
CAP - High Performace Computing Group
CNDS - Computer Networks and Distributed Systems
VIRTUOS - Virtualisation and Operating Systems

Participants