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ShadowHTM: Using a dual-bitcell L1 data cache to improve hardware transactional memory performance

Autor
Armejach, A.; Seyedi, A.; Titos, R.; Hur, I.; Unsal, O.; Cristal, A.; Valero, M.
Tipus d'activitat
Document cientificotècnic
Data
2010
Codi
UPC-DAC-RR-CAP-2010-30
Resum
In Hardware Transactional Memory (HTM) systems one of the key design dimensions is version management, which defines 'how' and 'where' speculative values are stored. Version management can be implemented either eagerly, storing speculative values in-place; or lazily, buffering speculative updates aside in specific hardware. However, both approaches suffer from performance penalties due to the inability to efficiently handle two versions of the same logical data. We introduce a dual-bitcell L1 d...
Paraules clau
Hardware, Performance, Transactional memory
Grup de recerca
CAP - Grup de Computació d'Altes Prestacions

Participants

  • Armejach, Adrià  (autor)
  • Seyedi, Azam  (autor)
  • Titos Gil, Rubén  (autor)
  • Hur, Ibrahim  (autor)
  • Unsal, Osman Sabri  (autor)
  • Cristal Kestelman, Adrián  (autor)
  • Valero Cortes, Mateo  (autor)