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Memory Hierarchies for Future HPC Architectures

Author
Garcia, V.
Type of activity
Theses
Other related units
Department of Computer Architecture
Defense's date
2017-10-02
URL
http://hdl.handle.net/2117/113684 Open in new window
Abstract
Efficiently managing the memory subsystem of modern multi/manycore architectures is increasingly becoming a challenge as systems grow in complexity and heterogeneity. In the field of high performance computing (HPC) in particular, where massively parallel architectures are used and input sets of several terabytes are common, careful management of the memory hierarchy is crucial to exploit the full computing power of these systems. The goal of this thesis is to provide computer architects with va...
Group of research
CAP - High Performace Computing Group
Citation
García Flores, V. "Memory hierarchies for future HPC architectures". Tesi doctoral, UPC, Departament d'Arquitectura de Computadors, 2017.

Participants

  • Ujaldón Martínez, Manuel  (chair)
  • Garcia Flores, Victor  (author)
  • Martorell Bofill, Xavier  (secretary)
  • Teixidó, Joaquin  (president)
  • Ayguade Parra, Eduard  (director)
  • Peña Monferrer, Antonio Jose  (director)
  • Kaeli, David  (president)

Attachments