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Suitability of FinFET introduction into eDRAM cells for operate at sub-threshold level

Author
Amat, E.; Calomarde, A.; Canal, R.; Rubio, A.
Type of activity
Presentation of work at congresses
Name of edition
27th International Symposium on Power and Timing Modeling, Optimization and Simulation
Date of publication
2017
Presentation's date
2017-09-04
Book of congress proceedings
27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS 2017): Thessaloniki, Greece, Sept. 25-27, 2017
First page
1
Last page
6
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
DOI
https://doi.org/10.1109/PATMOS.2017.8106951 Open in new window
Project funding
Multilevel approach to the reliability-aware design of analog and digital integrated circuits
Towards Trusted Low-Power Things: Devices, Circuits and Architectures
Repository
http://hdl.handle.net/2117/113578 Open in new window
URL
http://ieeexplore.ieee.org/document/8106951/ Open in new window
Abstract
This paper explores the feasibility, in terms of performance and reliability, of gain-cell embedded DRAM (eDRAM) to be operative at sub-threshold range, when they are implemented with 10 nm FinFET devices. The use of individual transistor resizing in order to achieve better cell performance (i.e. retention time, access time, and energy consumption) at the sub-VT operating level is studied. In this scenario, asymmetrically resizing the memory cell, since we modify the channel length of the write ...
Citation
Amat, E., Calomarde, A., Canal, R., Rubio, A. Suitability of FinFET introduction into eDRAM cells for operate at sub-threshold level. A: International Workshop on Power and Timing Modeling, Optimization and Simulation. "27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS 2017): Thessaloniki, Greece, Sept. 25-27, 2017". Thessaloniki: Institute of Electrical and Electronics Engineers (IEEE), 2017, p. 1-6.
Keywords
FinFET, eDRAM, reliability., single event upsets, sub-VT, variability
Group of research
HIPICS - High Performance Integrated Circuits and Systems
VIRTUOS - Virtualisation and Operating Systems

Participants