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MeRLiN: Exploiting dynamic instruction behavior for fast and accurate microarchitecture level reliability assessment

Author
Kaliorakis, M.; Gizopoulos, D.; Canal, R.; Gonzalez, A.
Type of activity
Presentation of work at congresses
Name of edition
44th International Symposium on Computer Architecture
Date of publication
2017
Presentation's date
2017-06-26
Book of congress proceedings
ISCA '17: Proceedings of the 44th Annual International Symposium on Computer Architecture
First page
241
Last page
254
Publisher
Association for Computing Machinery (ACM)
DOI
https://doi.org/10.1145/3140659.3080225 Open in new window
Repository
http://hdl.handle.net/2117/113966 Open in new window
URL
https://dl.acm.org/citation.cfm?id=3080225 Open in new window
Abstract
Early reliability assessment of hardware structures using microarchitecture level simulators can effectively guide major error protection decisions in microprocessor design. Statistical fault injection on microarchitectural structures modeled in performance simulators is an accurate method to measure their Architectural Vulnerability Factor (AVF) but requires excessively long campaigns to obtain high statistical significance. We propose MeRLiN1, a methodology to boost microarchitecture level in...
Citation
Kaliorakis, M., Gizopoulos, D., Canal, R., González, A. MeRLiN: Exploiting dynamic instruction behavior for fast and accurate microarchitecture level reliability assessment. A: International Symposium on Computer Architecture. "ISCA '17: Proceedings of the 44th Annual International Symposium on Computer Architecture". Toronto, ON: Association for Computing Machinery (ACM), 2017, p. 241-254.
Keywords
Architectural vulnerability factor, Fault injection, Microarchitecture level reliability estimation, Transient faults
Group of research
ARCO - Microarchitecture and Compilers
VIRTUOS - Virtualisation and Operating Systems

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