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HW/SW co-designed processors: Challenges, design choices and a simulation infrastructure for evaluation

Author
Kumar, R.; Cano, J.; Brankovic, A.; Pavlou, D.; Stavrou, K.; Gibert, E.; Martínez, A.; Gonzalez, A.
Type of activity
Presentation of work at congresses
Name of edition
2017 IEEE International Symposium on Performance Analysis of Systems and Software
Date of publication
2017
Presentation's date
2017-04-24
Book of congress proceedings
ISPASS 2017: IEEE International Symposium on Performance Analysis of Systems and Software: April 24-25, 2017, Santa Rosa, California
First page
185
Last page
194
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
DOI
https://doi.org/10.1109/ISPASS.2017.7975290 Open in new window
Repository
http://hdl.handle.net/2117/113961 Open in new window
URL
http://ieeexplore.ieee.org.recursos.biblioteca.upc.edu/abstract/document/7975290 Open in new window
Abstract
Improving single thread performance is a key challenge in modern microprocessors especially because the traditional approach of increasing clock frequency and deep pipelining cannot be pushed further due to power constraints. Therefore, researchers have been looking at unconventional architectures to boost single thread performance without running into the power wall. HW/SW co-designed processors like Nvidia Denver, are emerging as a promising alternative. However, HW/SW co-designed processors n...
Citation
Kumar, R., Cano, J., Brankovic, A., Pavlou, D., Stavrou, K., Gibert, E., Martínez, A., González, A. HW/SW co-designed processors: Challenges, design choices and a simulation infrastructure for evaluation. A: IEEE International Symposium on Performance Analysis of Systems and Software. "ISPASS 2017: IEEE International Symposium on Performance Analysis of Systems and Software: April 24-25, 2017, Santa Rosa, California". San Francisco, CA: Institute of Electrical and Electronics Engineers (IEEE), 2017, p. 185-194.
Keywords
Hardware-software codesign, Microprocessor chips, Performance evaluation
Group of research
ARCO - Microarchitecture and Compilers

Participants

  • Kumar, Rakesh  (author and speaker )
  • Cano, José  (author and speaker )
  • Brankovic, Aleksandar  (author and speaker )
  • Pavlou, Demos  (author and speaker )
  • Stavrou, Kyriakos  (author and speaker )
  • Gibert Codina, Enric  (author and speaker )
  • Martínez, Alejandro  (author and speaker )
  • Gonzalez Colas, Antonio Maria  (author and speaker )

Attachments