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Automatic prefetch and modulo scheduling transformations for the Cell BE architecture

Author
Vujic, N.; Gonzalez, M.; Martorell, X.; Ayguade, E.
Type of activity
Journal article
Journal
IEEE transactions on parallel and distributed systems
Date of publication
2010-04
Volume
21
Number
4
First page
494
Last page
505
DOI
https://doi.org/10.1109/TPDS.2009.97 Open in new window
URL
http://www.computer.org/portal/web/csdl/doi/10.1109/TPDS.2009.97 Open in new window
Abstract
Ease of programming is one of the main requirements for the broad acceptance of multicore systems without hardware support for transparent data transfer between local and global memories. Software cache is a robust approach to provide the user with a transparent view of the memory architecture; but this software approach can suffer from poor performance. In this paper, we propose a hierarchical, hybrid software-cache architecture that targets enabling prefetch techniques. Memory accesses are cla...
Keywords
Cache storage, Memory architecture, Microprocessor chips, Multiprocessing systems, Performance evaluation, Processor scheduling
Group of research
CAP - High Performace Computing Group

Participants