Loading...
Loading...

Go to the content (press return)

Review on suitable eDRAM configurations for next nano-metric electronics era

Author
Amat, E.; Canal, R.; Calomarde, A.; Rubio, A.
Type of activity
Journal article
Journal
International journal of the Society of Materials Engineering for Resources.The Society of Materials Engineering for Resources of Japan
Date of publication
2018-03
Volume
23
Number
1
First page
22
Last page
29
Project funding
Multilevel approach to the reliability-aware design of analog and digital integrated circuits
Towards Trusted Low-Power Things: Devices, Circuits and Architectures
Repository
http://hdl.handle.net/2117/119979 Open in new window
Abstract
We summarize most of our studies focused on the main reliability issues that can threat the gain-cells eDRAM behavior when it is simulated at the nano-metric device range has been collected in this review. So, to outperform their memory cell counterparts, we explored different technological proposals and operational regimes where it can be located. The best memory cell performance is observed for the 3T1D-eDRAM cell when it is based on FinFET devices. Both device variability and SEU appear as ke...
Citation
Amat, E., Canal, R., Calomarde, A., Rubio, A. Review on suitable eDRAM configurations for next nano-metric electronics era. "International journal of the Society of Materials Engineering for Resources.The Society of Materials Engineering for Resources of Japan", Març 2018, vol. 23, núm. 1, p. 22-29.
Keywords
FinFET, SEU, eDRAM, sub-VT
Group of research
HIPICS - High Performance Integrated Circuits and Systems
VIRTUOS - Virtualisation and Operating Systems

Participants

Attachments