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Full open defects in nanometric CMOS

Author
Rodriguez-Montanes, R.; Arumi, D.; Figueras, J.
Type of activity
Presentation of work at congresses
Name of edition
26th IEEE VLSI Test Symposium
Date of publication
2018
Book of congress proceedings
26th IEEE VLSI Test Symposium, 2008: VTS 2008; April 27, 2008-May 1, 2008, San Diego, California; proceedings
First page
119
Last page
124
DOI
https://doi.org/10.1109/VTS.2008.31 Open in new window
URL
https://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=4511672 Open in new window
Abstract
Full open defects on the interconnect lines cause the broken wires to become floating. The voltage of a floating line depends on its topological characteristics, namely: parasitic capacitances to neighbouring structures, transistor capacitances of the downstream gate(s) and the trapped charge. However, in nanometric CMOS technologies, the oxide thickness is reduced below a few tens of Aring causing the gate tunnelling leakage to strongly impact the behaviour of defective circuits with full open ...
Keywords
CMOS, gate leakage current, interconnect open
Group of research
CRnE - Barcelona Research Center in Multiscale Science and Engineering
QINE - Low Power Design, Test, Verification and Security ICs

Participants