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The design and performance of a conflict-avoiding cache

Author
Topham, N.; Gonzalez, A.; González, J.
Type of activity
Presentation of work at congresses
Name of edition
30th Annual International Symposium on Microarchitecture
Date of publication
1997
Presentation's date
1997-12-01
Book of congress proceedings
Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture: December 1-3, 1997, Research Triangle Park, North Carolina: proceedings
First page
71
Last page
80
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
DOI
https://doi.org/10.1109/MICRO.1997.645799 Open in new window
Repository
http://hdl.handle.net/2117/101279 Open in new window
URL
http://ieeexplore.ieee.org/document/645799/ Open in new window
Abstract
High performance architectures depend heavily on efficient multi-level memory hierarchies to minimize the cost of accessing data. This dependence will increase with the expected increases in relative distance to main memory. There have been a number of published proposals for cache conflict-avoidance schemes. We investigate the design and performance of conflict-avoiding cache architectures based on polynomial modulus functions, which earlier research has shown to be highly effective at reducing...
Citation
Topham, N., González, A., González, J. The design and performance of a conflict-avoiding cache. A: Annual IEEE/ACM International Symposium on Microarchitecture. "MICRO 30: proceedings of the 30th Annual ACM/IEEE International Symposium on Microarchitecture". San Francisco: Institute of Electrical and Electronics Engineers (IEEE), 1997, p. 71-80.
Keywords
Cache storage, Instruction sets, Memory architecture, Parallel architectures, Parallel machines, Performance evaluation
Group of research
ARCO - Microarchitecture and Compilers

Participants

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