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A novel register renaming technique for out-of-order processors

Author
Tabani, H.; Arnau, J.; Tubella, J.; Gonzalez, A.
Type of activity
Presentation of work at congresses
Name of edition
24th International Symposium on High-Performance Computer Architecture
Date of publication
2018
Presentation's date
2018-02-24
Book of congress proceedings
2018 IEEE International Symposium on High Performance Computer Architecture (HPCA 2018): Vienna, Austria; 24-28 February 2018
First page
259
Last page
270
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
DOI
https://doi.org/10.1109/HPCA.2018.00031 Open in new window
Project funding
Intelligent, Ubiquitous and Energy-Efficient Computing Systems
Microarchitecture and Compilers for Future Processors III
Repository
http://hdl.handle.net/2117/122264 Open in new window
URL
https://ieeexplore.ieee.org/document/8327014 Open in new window
Abstract
Modern superscalar processors support a large number of in-flight instructions, which requires sizeable register files. Conventional register renaming techniques allocate a new storage location, i.e. physical register, for every instruction whose destination is a logical register in order to remove false dependences. Physical registers are released in a conservative manner when the same logical register is redefined. For this reason, many cycles may happen between the last read and the release o...
Citation
Tabani, H., Arnau, J., Tubella, J., Gonzalez Colas, A. A novel register renaming technique for out-of-order processors. A: International Symposium on High-Performance Computer Architecture. "2018 IEEE International Symposium on High Performance Computer Architecture (HPCA 2018): Vienna, Austria; 24-28 February 2018". Institute of Electrical and Electronics Engineers (IEEE), 2018, p. 259-270.
Keywords
Computer architecture, In-flight instructions, Out-of-order processors, Physical registers, Precise exceptions, Producer consumers, Register file, Register files, Register renaming, Register renaming supercomputers, Superscalar processor
Group of research
ARCO - Microarchitecture and Compilers

Participants