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Reducing the complexity of the issue logic

Author
Canal, R.; Gonzalez, A.
Type of activity
Presentation of work at congresses
Name of edition
15th ACM International Conference on Supercomputing
Date of publication
2001
Presentation's date
2001
Book of congress proceedings
Proceedings of the 15th international conference on Supercomputing, ICS 2001: Sorrento, Napoli, Italy, June 16-21, 2001
First page
312
Last page
320
DOI
https://doi.org/10.1145/377792.377854 Open in new window
URL
http://dl.acm.org/citation.cfm?doid=377792.377854 Open in new window
Abstract
The issue logic of dynamically scheduled superscalar processors is one of their most complex and power-consuming parts. In this paper we present alternative issue-logic designs that are much simpler than the traditional scheme while they retain most of its ability to exploit ILP. These alternative schemes are based on the observation that most values produced by a program are used by very few instructions, and the latencies of most operation are deterministic.
Keywords
Complexityeffective design, Instruction issue logic, Out-of-order issue, Wide-issue superscalar
Group of research
ARCO - Microarchitecture and Compilers
VIRTUOS - Virtualisation and Operating Systems

Participants