Loading...
Loading...

Go to the content (press return)

Memory controller for vector processor

Author
Hussain, T.; Palomar, O.; Unsal, O.; Cristal, A.; Ayguade, E.
Type of activity
Journal article
Journal
Journal of signal processing systems
Date of publication
2018-11
Volume
90
Number
11
First page
1533
Last page
1549
DOI
10.1007/s11265-016-1215-5
Repository
http://hdl.handle.net/2117/130124 Open in new window
URL
https://link.springer.com/article/10.1007%2Fs11265-016-1215-5 Open in new window
Abstract
To manage power and memory wall affects, the HPC industry supports FPGA reconfigurable accelerators and vector processing cores for data-intensive scientific applications. FPGA based vector accelerators are used to increase the performance of high-performance application kernels. Adding more vector lanes does not affect the performance, if the processor/memory performance gap dominates. In addition if on/off-chip communication time becomes more critical than computation time, causes performance ...
Citation
Hussain, T. [et al.]. Memory controller for vector processor. "Journal of signal processing systems", Novembre 2018, vol. 90, núm. 11, p. 1533-1549.
Keywords
SDRAM controller, Scalar core, Vector processor
Group of research
CAP - High Performace Computing Group

Participants

  • Hussain, Tassadaq  (author)
  • Palomar, Oscar  (author)
  • Unsal, Osman Sabri  (author)
  • Cristal Kestelman, Adrián  (author)
  • Ayguade Parra, Eduard  (author)

Attachments