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Graph-partitioning based instruction scheduling for clustered processors

Author
Aleta, A.; Codina, J.M.; Sanchez, F.; Gonzalez, A.
Type of activity
Presentation of work at congresses
Name of edition
34th Annual ACM/IEEE International Symposium on Microarchitecture
Date of publication
2001
Presentation's date
2001
Book of congress proceedings
34th ACM/IEEE International Symposium on Microarchitecture, 2001, MICRO-34: proceedings
First page
150
Last page
159
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
DOI
https://doi.org/10.1109/MICRO.2001.991114 Open in new window
Repository
http://hdl.handle.net/2117/96793 Open in new window
URL
http://ieeexplore.ieee.org/document/991114/ Open in new window
Abstract
This paper presents a novel scheme to schedule loops for clustered microarchitectures. The scheme is based on a preliminary cluster assignment phase implemented through graph partitioning techniques followed by a scheduling phase that integrates register allocation and spill code generation. The graph partitioning scheme is shown to be very effective due to its global view of the whole code while the partition is generated. Results show a significant speedup when compared with previously propose...
Citation
Aleta, A., Codina, J.M., Sanchez, F., Gonzalez, A. Graph-partitioning based instruction scheduling for clustered processors. A: Annual IEEE/ACM International Symposium on Microarchitecture. "34th ACM/IEEE International Symposium on Microarchitecture, 2001, MICRO-34: proceedings". Austin: Institute of Electrical and Electronics Engineers (IEEE), 2001, p. 150-159.
Keywords
Delay, Digital signal processing, Energy consumption, Job shop scheduling, Microarchitecture, Processor scheduling, Transistors, VLIW, Wires
Group of research
ARCO - Microarchitecture and Compilers

Participants

  • Aleta Ortega, Alexandre  (author and speaker )
  • Codina Viñas, Josep M  (author and speaker )
  • Sanchez Navarro, F.Jesus  (author and speaker )
  • Gonzalez Colas, Antonio Maria  (author and speaker )

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