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SAMIE-LSQ: set-associative multiple-instruction entry load/store queue

Author
Abella, J.; Gonzalez, A.
Type of activity
Presentation of work at congresses
Name of edition
20th IEEE International Parallel and Distributed Processing Symposium
Date of publication
2006
Presentation's date
2006
Book of congress proceedings
Proceeding of the 20th IEEE International Parallel & Distributed Processing Symposium
First page
1
Last page
10
Publisher
IEEE Computer Society
DOI
https://doi.org/10.1109/IPDPS.2006.1639290 Open in new window
Repository
http://hdl.handle.net/2117/101144 Open in new window
URL
http://ieeexplore.ieee.org/document/1639290/ Open in new window
Abstract
The load/store queue (LSQ) is one of the most complex parts of contemporary processors. Its latency is critical for the processor performance and it is usually one of the processor hotspots. This paper presents a highly banked, set-associative, multiple-instruction entry LSQ (SAMIE-LSQ,) that achieves high performance with small energy requirements. The SAMIE-LSQ classifies the memory instructions (loads and stores) based on the address to be accessed, and groups those instructions accessing the...
Citation
Abella, J., González, A. SAMIE-LSQ: set-associative multiple-instruction entry load/store queue. A: IEEE International Parallel and Distributed Processing Symposium. "Proceeding of the 20th IEEE International Parallel & Distributed Processing Symposium". Ixia, Rodes: IEEE Computer Society, 2006, p. 1-10.
Keywords
Computer architecture, Concrete, Cooling, Costs, Delay, Pipelines, Power dissipation
Group of research
ARCO - Microarchitecture and Compilers

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