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A fault-tolerant last level cache for CMPs operating at ultra-low voltage

Author
Ferrerón, A.; Alastruey, J.; Suárez, D.; Monreal, T.; Ibáñez , P.; Viñals, V.
Type of activity
Journal article
Journal
Journal of parallel and distributed computing
Date of publication
2019-03
Volume
125
First page
31
Last page
44
DOI
https://doi.org/10.1016/j.jpdc.2018.10.010 Open in new window
Project funding
(TIN2016-76635-C2-1-R) Arquitectura y programación de computadores escalables de alto rendimiento y bajo consumo (APCE)
Computación de Altas Prestaciones VII
Repository
http://hdl.handle.net/2117/127595 Open in new window
URL
https://www.sciencedirect.com/science/article/pii/S0743731518307810 Open in new window
Abstract
Voltage scaling to values near the threshold voltage is a promising technique to hold off the many-core power wall. However, as voltage decreases, some SRAM cells are unable to operate reliably and show a behavior consistent with a hard fault. Block disabling is a micro-architectural technique that allows low-voltage operation by deactivating faulty cache entries, at the expense of reducing the effective cache capacity. In the case of the last-level cache, this capacity reduction leads to an inc...
Citation
Ferrerón, A. [et al.]. A fault-tolerant last level cache for CMPs operating at ultra-low voltage. "Journal of parallel and distributed computing", Març 2019, vol. 125, p. 31-44.
Keywords
Cache management, Near-threshold voltage, On-chip caches, SRAM reliability
Group of research
CAP - High Performace Computing Group

Participants

  • Ferrerón, Alexandra  (author)
  • Alastruey, Jesús  (author)
  • Suárez Gracía, Dario  (author)
  • Monreal Arnal, Teresa  (author)
  • Ibáñez Marín, Pablo Enrique  (author)
  • Viñals Yúfera, Víctor  (author)