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Via-configurable transistors array: a regular design technique to improve ICs yield

Author
Pons, M.; Moll, F.; Rubio, A.; Abella, J.; Vera, F.J.; Gonzalez, A.
Type of activity
Presentation of work at congresses
Name of edition
2nd IEEE International Workshop on Design for Manufacturability and Yield
Date of publication
2007
Presentation's date
2007
Book of congress proceedings
2nd IEEE International Workshop on Design for Manufacturability and Yield 2007 (DFM&Y): October 25-26, 2007, Santa Clara Convention Center, California, USA
First page
1
Last page
8
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Repository
http://hdl.handle.net/2117/105838 Open in new window
Abstract
Process variations are a major bottleneck for digital CMOS integrated circuits manufacturability and yield. That is why regular techniques with different degrees of regularity are emerging as possible solutions. Our proposal is a new regular layout design technique called Via-Configurable Transistors Array (VCTA) that pushes to the limit circuit layout regularity for devices and interconnects in order to maximize regularity benefits. VCTA is predicted to perform worse than the Standard Cell app...
Citation
Pons, M., Moll, F., Rubio, A., Abella, J., Vera, F.J., González, A. Via-configurable transistors array: a regular design technique to improve ICs yield. A: IEEE International Workshop on Design for Manufacturability and Yield. "2nd IEEE International Workshop on Design for Manufacturability and Yield 2007 (DFM&Y): October 25-26, 2007, Santa Clara Convention Center, California, USA". Santa Clara, CA: Institute of Electrical and Electronics Engineers (IEEE), 2007, p. 1-8.
Keywords
CMOS, DFM, DSM, Digital ICs, Regular designs, VCTA, Via-configurable transistors array, Yield
Group of research
ARCO - Microarchitecture and Compilers
HIPICS - High Performance Integrated Circuits and Systems

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