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Reducing wire delay penalty through value prediction

Author
Parcerisa, Joan-Manuel; Gonzalez, A.
Type of activity
Presentation of work at congresses
Name of edition
33rd Annual ACM/IEEE International Symposium on Microarchitecture
Date of publication
2000
Presentation's date
2000-12-10
Book of congress proceedings
33rd Annual ACM/IEEE International Symposium on Microarchitecture: MICRO-33, 2000: 10-13 december 2000: Monterey, California, USA: proceedings
First page
317
Last page
326
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
DOI
https://doi.org/10.1109/MICRO.2000.898081 Open in new window
Repository
http://hdl.handle.net/2117/101126 Open in new window
URL
http://ieeexplore.ieee.org/document/898081/ Open in new window
Abstract
In this paper we show that value prediction can be used to avoid the penalty of long wire delays by predicting the data that is communicated through these long wires and validating the prediction locally where the value is produced. Only in the case of misprediction, the long wire delay is experienced. We apply this concept to a clustered microarchitecture in order to reduce inter-cluster communication. The predictability of values provides the dynamic instruction partitioning hardware with less...
Citation
Parcerisa, J.M., González, A. Reducing wire delay penalty through value prediction. A: Annual IEEE/ACM International Symposium on Microarchitecture. "33rd Annual ACM/IEEE International Symposium on Microarchitecture: MICRO-33, 2000: 10-13 december 2000: Monterey, California, USA: proceedings". Monterey, California: Institute of Electrical and Electronics Engineers (IEEE), 2000, p. 317-326.
Keywords
Delays, Workstation clusters
Group of research
ARCO - Microarchitecture and Compilers

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