Loading...
Loading...

Go to the content (press return)

Layout-aware gate duplication and buffer insertion

Author
Bañeres, D.; Cortadella, J.; Kishinevsky, M.
Type of activity
Presentation of work at congresses
Name of edition
Design, Automation and Test in Europe Conference and Exhibition 2007
Date of publication
2007
Book of congress proceedings
2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007: Nice, France, April 16-20, 2007
First page
1367
Last page
1372
DOI
10.1109/DATE.2007.364488
URL
https://dl.acm.org/citation.cfm?id=1266664 Open in new window
Abstract
An approach for layout-aware interconnect optimization is presented. It is based on the combination of three sub-problems into the same framework: gate duplication, buffer insertion and placement. Different techniques to control the combinatorial explosion are proposed. The experimental results show tangible benefits in delay that endorse the suitability of integrating the three sub-problems in the same framework. The results also corroborate the increasing relevance of interconnect optimization...
Keywords
Buffer circuits, Delays, Dynamic programming, Integrated circuit interconnections, Integrated circuit layout
Group of research
ALBCOM - Algorithms, Computational Biology, Complexity and Formal Methods

Participants