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Direct instruction wakeup for out-of-order processors

Author
Ramirez, M.; Cristal, A.; Veidenbaum, A.; Villa, L.; Valero, M.
Type of activity
Presentation of work at congresses
Name of edition
International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems 2004
Date of publication
2004
Presentation's date
2004-01
Book of congress proceedings
Innovative Architecture for Future Generation High-Performance Processors and Systems: IWIA 2004: 12-14 January 2004, Maui, Hawaii: proceedings
First page
2
Last page
9
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
DOI
https://doi.org/10.1109/IWIA.2004.10002 Open in new window
Repository
http://hdl.handle.net/2117/111579 Open in new window
URL
http://ieeexplore.ieee.org/document/1410675/ Open in new window
Abstract
Instruction queues consume a significant amount of power in high-performance processors, primarily due to instruction wakeup logic access to the queue structures. The wakeup logic delay is also a critical timing parameter. This paper proposes a new queue organization using a small number of successor pointers plus a small number of dynamically allocated full successor bit vectors for cases with a larger number of successors. The details of the new organization are described and it is shown to ac...
Citation
Ramírez, M., Cristal, A., Veidenbaum, A., Villa, L., Valero, M. Direct instruction wakeup for out-of-order processors. A: International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems. "Innovative Architecture for Future Generation High-Performance Processors and Systems: IWIA 2004: 12-14 January 2004, Maui, Hawaii: proceedings". Maui, Hawaii: Institute of Electrical and Electronics Engineers (IEEE), 2004, p. 2-9.
Keywords
CAM, Direct wakeup, Issue queue, Low-power, Out-of-order processors, Wakeup instructions
Group of research
CAP - High Performace Computing Group

Participants

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