Loading...
Loading...

Go to the content (press return)

Virtual registers

Author
Gonzalez, A.; Valero, M.; González, J.; Monreal, T.
Type of activity
Presentation of work at congresses
Name of edition
4th International Conference on High-Performance Computing
Date of publication
1997
Presentation's date
1997
Book of congress proceedings
Fourth International Conference on High-Performance Computing: December 18-21, 1997, Bangalore, India: proceedings
First page
364
Last page
369
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
DOI
https://doi.org/10.1109/HIPC.1997.634516 Open in new window
Repository
http://hdl.handle.net/2117/105578 Open in new window
URL
http://ieeexplore.ieee.org/document/634516/ Open in new window
Abstract
The number of physical registers is one of the critical issues of current superscalar out-of-order processors. Conventional architectures allocate, in the decoding stage, a new storage location (e.g. a physical register) for each operation that has a destination register. When an instruction is committed, it frees the physical register allocated to the previous instruction that had the same destination logical register. Thus, an additional register (i.e. in addition to the number of logical regi...
Citation
González, A., Valero, M., González, J., Monreal, T. Virtual registers. A: International Conference on High-Performance Computing. "Fourth International Conference on High-Performance Computing: December 18-21, 1997, Bangalore, India: proceedings". Bangalore: Institute of Electrical and Electronics Engineers (IEEE), 1997, p. 364-369.
Keywords
Computer architecture, Decoding, Multiprocessing systems, Storage allocation, Virtual storage
Group of research
ARCO - Microarchitecture and Compilers
CAP - High Performace Computing Group

Participants

Attachments