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The synergy of multithreading and access/execute decoupling

Author
Parcerisa, Joan-Manuel; Gonzalez, A.
Type of activity
Presentation of work at congresses
Name of edition
Fifth International Symposium on High-Performance Computer Architecture
Date of publication
1999
Presentation's date
1999
Book of congress proceedings
Fifth International Symposium on High-Performance Computer Architecture: January 9-13,1999, Orlando, Florida: proceedings
First page
59
Last page
63
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
DOI
https://doi.org/10.1109/HPCA.1999.744329 Open in new window
Repository
http://hdl.handle.net/2117/105279 Open in new window
URL
http://ieeexplore.ieee.org/document/744329/ Open in new window
Abstract
This work presents and evaluates a novel processor microarchitecture which combines two paradigms: access/execute decoupling and simultaneous multithreading. We investigate how both techniques complement each other: while decoupling features an excellent memory latency hiding efficiency, multithreading supplies the in-order issue stage with enough ILP to hide the functional unit latencies. Its partitioned layout, together with its in-order issue policy makes it potentially less complex, in terms...
Citation
Parcerisa, J.M., González, A. The synergy of multithreading and access/execute decoupling. A: International Symposium on High-Performance Computer Architecture. "Fifth International Symposium on High-Performance Computer Architecture: January 9-13,1999, Orlando, Florida: proceedings". Orlando: Institute of Electrical and Electronics Engineers (IEEE), 1999, p. 59-63.
Keywords
Delays, Multi-threading, Parallel architectures, Processor scheduling, Virtual machines
Group of research
ARCO - Microarchitecture and Compilers

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