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Heterogeneous way-size cache

Author
Abella, J.; Gonzalez, A.
Type of activity
Presentation of work at congresses
Name of edition
20th ACM International Conference on Supercomputing
Date of publication
2006
Presentation's date
2006
Book of congress proceedings
ICS'06: proceedings of the 20th Annual International Conference on Supercomputing
First page
239
Last page
248
DOI
https://doi.org/10.1145/1183401.1183436 Open in new window
URL
http://dl.acm.org/citation.cfm?id=1183401.1183436 Open in new window
Abstract
Set-associative cache architectures are commonly used. These caches consist of a number of ways, each of the same size. We have observed that the different ways have very different utilization, which motivates the design of caches with heterogeneous way sizes. This can potentially result in higher performance for the same area, better capabilities to implement dynamically adaptive schemes, and more flexibility for choosing the size of the cache.This paper proposes a novel cache architecture, the...
Keywords
Adaptive, Cache memories, Low power, Set-associative
Group of research
ARCO - Microarchitecture and Compilers

Participants