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Heterogeneous clustered VLIW microarchitectures

Author
Aleta, A.; Codina, J.M.; Gonzalez, A.; Kaeli, D.
Type of activity
Presentation of work at congresses
Name of edition
2007 International Symposium on Code Generation and Optimization
Date of publication
2007
Presentation's date
2007
Book of congress proceedings
International Symposium on Code Generation and Optimization, CGO 2007: 11-14 March 2007, San Jose, California
First page
354
Last page
366
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
DOI
https://doi.org/10.1109/CGO.2007.15 Open in new window
Repository
http://hdl.handle.net/2117/96796 Open in new window
URL
http://ieeexplore.ieee.org/document/4145127/ Open in new window
Abstract
Increasing performance, while at the same time reducing power consumption, is a major design tradeoff in current microprocessors. In this paper, we investigate the potential of using a heterogeneous clustered VLIW microarchitecture. In the proposed microarchitecture, each cluster, the interconnection network and the supporting memory hierarchy can run at different frequencies and voltages. Some of the clusters can then be configured to be performance-oriented and run at high frequency, while the...
Citation
Aleta, A., Codina, J., González, A., Kaeli, D. Heterogeneous clustered VLIW microarchitectures. A: International Symposium on Code Generation and Optimization. "International Symposium on Code Generation and Optimization, CGO 2007: 11-14 March 2007, San Jose, California". San Jose, CA: Institute of Electrical and Electronics Engineers (IEEE), 2007, p. 354-366.
Keywords
Delay, Energy consumption, Frequency, Microarchitecture, Multiprocessor interconnection networks, Processor scheduling, VLIW, Voltage
Group of research
ARCO - Microarchitecture and Compilers

Participants

  • Aleta Ortega, Alexandre  (author and speaker )
  • Codina Viñas, Josep M  (author and speaker )
  • Gonzalez Colas, Antonio Maria  (author and speaker )
  • Kaeli, David  (author and speaker )

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