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An optimized front-end physical register file with banking and writeback filtering

Author
Pericas, M.; González, R.; Cristal, A.; Veidenbaum, A.; Valero, M.
Type of activity
Presentation of work at congresses
Name of edition
Fourth Workshop on Power-Aware Computer Systems
Date of publication
2004
Presentation's date
2004-12
Book of congress proceedings
Power-Aware Computer Systems: 4th International Workshop, PACS 2004: Portland, OR, USA, December 5, 2004: revised selected papers
First page
1
Last page
14
DOI
https://doi.org/10.1007/11574859_1 Open in new window
URL
https://link.springer.com/chapter/10.1007/11574859_1 Open in new window
Abstract
Register file design is one of the critical issues facing designers of out–of–order processors. Scaling up its size and number of ports with issue width and instruction window size is difficult in terms of both performance and power consumption. Two types of register file architectures have been proposed in the past: a future logical file and a centralized physical file. The centralized register file does not scale well but allows fast branch mis–prediction recovery. The Future File scales...
Keywords
Computer power supplies, Logic design, Memory architecture, Microprocessor chips
Group of research
CAP - High Performace Computing Group

Participants

  • Pericas Gleim, Miquel  (author and speaker )
  • González Garcia, Ruben  (author and speaker )
  • Cristal Kestelman, Adrian  (author and speaker )
  • Veidenbaum, Alex  (author and speaker )
  • Valero Cortes, Mateo  (author and speaker )