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Improving branch prediction and predicated execution in out-of-order processors

Author
Quiñones, E.; Parcerisa, Joan-Manuel; Gonzalez, A.
Type of activity
Presentation of work at congresses
Name of edition
13th International Symposium on High-Performance Computer Architecture
Date of publication
2007
Presentation's date
2007
Book of congress proceedings
2007 IEEE 13th International Symposium on High Performance Computer Architecture
First page
75
Last page
84
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
DOI
https://doi.org/10.1109/HPCA.2007.346186 Open in new window
Repository
http://hdl.handle.net/2117/96823 Open in new window
URL
http://ieeexplore.ieee.org/document/4147649/ Open in new window
Abstract
If-conversion is a compiler technique that reduces the misprediction penalties caused by hard-to-predict branches, transforming control dependencies into data dependencies. Although it is globally beneficial, it has a negative side-effect because the removal of branches eliminates useful correlation information necessary for conventional branch predictors. The remaining branches may become harder to predict. However, in predicated ISAs with a compare-branch model, the correlation information not...
Citation
Quiñones, E., Parcerisa, Joan-Manuel, González, A. Improving branch prediction and predicated execution in out-of-order processors. A: International Symposium on High-Performance Computer Architecture. "2007 IEEE 13th International Symposium on High Performance Computer Architecture". Phoenix, AZ: Institute of Electrical and Electronics Engineers (IEEE), 2007, p. 75-84.
Keywords
Accuracy, Computer aided instruction, Costs, Degradation, Hardware, Instruction sets, Out of order, Pipelines, Proposals, Registers
Group of research
ARCO - Microarchitecture and Compilers

Participants

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