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Instruction-level parallelism and computer architecture

Author
Ayguade, E.; Dahlgren, F.; Christine, E.; Espasa, R.; Guang, R.; Muller, H.; Sakellariou, R.; Seznec, A.
Type of activity
Presentation of work at congresses
Name of edition
7th International European Conference on Parallel and Distributed Computing
Date of publication
2001
Presentation's date
2001-08
Book of congress proceedings
Euro-Par 2001 Parallel Processing: 7th International Euro-Par Conference: Manchester, UK, August 28–31, 2001: proceedings
First page
385
Last page
385
DOI
https://doi.org/10.1007/3-540-44681-8_56 Open in new window
URL
http://link.springer.com/chapter/10.1007%2F3-540-44681-8_56 Open in new window
Abstract
The papers presented in this combined topic consider issues related to the broad theme of computer architecture research. The program reflects the current emphasis of research on the exploitation of instruction-level parallelism and thread-level parallelism, with the papers presented covering several important aspects on both approaches: branch prediction, speculative multitheading, pipelining and superscalar architecture design, SIMD extensions, and dynamic scheduling issues in multithreaded ar...
Group of research
CAP - High Performace Computing Group

Participants

  • Ayguade Parra, Eduard  (author and speaker )
  • Dahlgren, Fredrik  (author and speaker )
  • Christine, Eisenbeis  (author and speaker )
  • Espasa Sans, Roger  (author and speaker )
  • Guang, R Gao  (author and speaker )
  • Muller, Henk  (author and speaker )
  • Sakellariou, Rizos  (author and speaker )
  • Seznec, André  (author and speaker )